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febv1_debug [2018/11/09 05:23]
acqilc [Injection tests]
febv1_debug [2021/07/10 23:21] (current)
Line 112: Line 112:
 ====  2018/11/09 Status & plans ==== ====  2018/11/09 Status & plans ====
  
- * Debugging Petiroc FSM (deadlock). Lengthly due to compilation time with 48 channels (2h) + ​* ​''​Debugging Petiroc FSM'' ​(deadlock). Lengthly due to compilation time with 48 channels (2h) 
   ​   ​
- * Next week:+ ​* ​''​Next week''​:
  
     * Complete time calibration     * Complete time calibration
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       * Repeat noise and calibration tests       * Repeat noise and calibration tests
       * Check efficiency curves and position resolution       * Check efficiency curves and position resolution
-  ​* Before Xmas break:+ 
 + 
 + ''​Before Xmas break''​: 
 + 
     * Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs)     * Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs)
     * Re submit the board with all corrections     * Re submit the board with all corrections
       * Confirm all the fixes before submitting V2       * Confirm all the fixes before submitting V2
       * Will be used for R&D RPCs       * Will be used for R&D RPCs
 +
 +
 +====  2018/11/11 Debugging ====
 +
 +
 +Still unstable PETIROC FSM with 48 channels
 +
 +  * Working with small time window or with low rate, dead lock in all other cases
 +  * Working with 16 channels
 +
 +
febv1_debug.1541740980.txt.gz · Last modified: 2021/07/10 23:20 (external edit)