• Missing control signals on regulator ⇒ by passed hardwarely
• One missing pull up on NOR32 per ASIC ⇒ Fixed externally
• HDMI signals direction ⇒ Use alternative signal entries on FPGA and patch MDCC accordingly
• 11 Mhz calibration clock missing ⇒ oscillator added on spare entry
• Jitter-cleaner chip unstability ⇒ By passed, used either an additional 40 Mhz oscillator or MDCC clock directly

• Signal TAP (multi channels internal logic analyzer) unstabilties
  • Initially we thought it is firmware related. Lot of time lost in trying to understand fluctuant behaviours
• Identified the source to a 400 MHz clock unstabilities ⇒ Internal to the FPGA
• Vcc core drops from 1.1 V to 0.95 V when more than 24 channels used
  • We first change the regulator ⇒ same problem
  • Routing issue: Strip line from regulator to FPGA too resistive ⇒ bring directly the 1.1 V to the FPGA ⇒ SOLVED

Carefull: The 2 chips don't have the same mapping

It is functionnal but no possibility to modulate the FPGA output voltage ⇒ No pedestal/gain curve. Patch with additional buffers will be tested soon

Time calibration feasible.

* Debugging Petiroc FSM (deadlock). Lengthly due to compilation time with 48 channels (2h)

* Next week:

• Complete time calibration
• Re test ToT version
• Transfer the board to Cern and connect it on the return chamber (additional boards are still in cabling since some components are now missing in the cabling company)
  • Repeat noise and calibration tests
  • Check efficiency curves and position resolution

* Before Xmas break:

• Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs)
• Re submit the board with all corrections
  • Confirm all the fixes before submitting V2
  • Will be used for R&D RPCs

Still unstable PETIROC FSM with 48 channels

• Working with small time window or with low rate, dead lock in all other cases
• Working with 16 channels