febv1_debug
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febv1_debug [2018/11/09 05:11] acqilc [Injection tests] |
febv1_debug [2021/07/10 23:21] (current) |
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| Time calibration feasible. | Time calibration feasible. | ||
| - | ==== --- //[[laurent.mirabito@gmail.com|DAQ user]] 2018/11/09 06:10// | + | ==== 2018/11/09 Status & plans ==== |
| - | ==== | + | |
| + | * ''Debugging Petiroc FSM'' (deadlock). Lengthly due to compilation time with 48 channels (2h) | ||
| + | |||
| + | * ''Next week'': | ||
| + | |||
| + | * Complete time calibration | ||
| + | * Re test ToT version | ||
| + | * Transfer the board to Cern and connect it on the return chamber (additional boards are still in cabling since some components are now missing in the cabling company) | ||
| + | * Repeat noise and calibration tests | ||
| + | * Check efficiency curves and position resolution | ||
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| + | |||
| + | * ''Before Xmas break'': | ||
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| + | |||
| + | * Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs) | ||
| + | * Re submit the board with all corrections | ||
| + | * Confirm all the fixes before submitting V2 | ||
| + | * Will be used for R&D RPCs | ||
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| + | ==== 2018/11/11 Debugging ==== | ||
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| + | Still unstable PETIROC FSM with 48 channels | ||
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| + | * Working with small time window or with low rate, dead lock in all other cases | ||
| + | * Working with 16 channels | ||
febv1_debug.1541740267.txt.gz · Last modified: 2021/07/10 23:20 (external edit)
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