febv1_debug
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
febv1_debug [2018/11/08 13:01] acqilc |
febv1_debug [2021/07/10 23:21] (current) |
||
|---|---|---|---|
| Line 84: | Line 84: | ||
| {{ :oct2018:run745460_allstrip2_2.png?600 |}} | {{ :oct2018:run745460_allstrip2_2.png?600 |}} | ||
| + | |||
| + | == FEBv2_7 channel per channel 745463 == | ||
| + | |||
| + | {{ :oct2018:run745463_allstrip2_1.png?600 |}} | ||
| + | |||
| + | {{ :oct2018:run745463_allstrip2_2.png?600 |}} | ||
| + | |||
| + | == FEBv2_8 channel per channel 745464 == | ||
| + | |||
| + | {{ :oct2018:run745464_allstrip2_1.png?600 |}} | ||
| + | |||
| + | {{ :oct2018:run745464_allstrip2_2.png?600 |}} | ||
| + | |||
| + | == FEBv2_8 all channels 745465 == | ||
| + | |||
| + | {{ :oct2018:run745465_allstrip2_1.png?600 |}} | ||
| + | |||
| + | {{ :oct2018:run745465_allstrip2_2.png?600 |}} | ||
| + | |||
| + | ==== Injection tests ==== | ||
| + | === Injection board === | ||
| + | |||
| + | It is functionnal but no possibility to modulate the FPGA output voltage ⇒ No pedestal/gain curve. Patch with additional buffers will be tested soon | ||
| + | |||
| + | Time calibration feasible. | ||
| + | |||
| + | ==== 2018/11/09 Status & plans ==== | ||
| + | |||
| + | * ''Debugging Petiroc FSM'' (deadlock). Lengthly due to compilation time with 48 channels (2h) | ||
| + | | ||
| + | * ''Next week'': | ||
| + | |||
| + | * Complete time calibration | ||
| + | * Re test ToT version | ||
| + | * Transfer the board to Cern and connect it on the return chamber (additional boards are still in cabling since some components are now missing in the cabling company) | ||
| + | * Repeat noise and calibration tests | ||
| + | * Check efficiency curves and position resolution | ||
| + | |||
| + | |||
| + | * ''Before Xmas break'': | ||
| + | |||
| + | |||
| + | * Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs) | ||
| + | * Re submit the board with all corrections | ||
| + | * Confirm all the fixes before submitting V2 | ||
| + | * Will be used for R&D RPCs | ||
| + | |||
| + | |||
| + | ==== 2018/11/11 Debugging ==== | ||
| + | |||
| + | |||
| + | Still unstable PETIROC FSM with 48 channels | ||
| + | |||
| + | * Working with small time window or with low rate, dead lock in all other cases | ||
| + | * Working with 16 channels | ||
| + | |||
febv1_debug.1541682109.txt.gz · Last modified: 2021/07/10 23:20 (external edit)
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 4.0 International
