febv1_debug
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febv1_debug [2018/11/08 10:49] acqilc créée |
febv1_debug [2021/07/10 23:21] (current) |
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| * Jitter-cleaner chip unstability ⇒ By passed, used either an additional 40 Mhz oscillator or MDCC clock directly | * Jitter-cleaner chip unstability ⇒ By passed, used either an additional 40 Mhz oscillator or MDCC clock directly | ||
| + | |||
| + | ===== Issue with high (>24) number of channels ===== | ||
| + | |||
| + | * Signal TAP (multi channels internal logic analyzer) unstabilties | ||
| + | * Initially we thought it is firmware related. Lot of time lost in trying to understand fluctuant behaviours | ||
| + | * Identified the source to a 400 MHz clock unstabilities ⇒ Internal to the FPGA | ||
| + | * Vcc core drops from 1.1 V to 0.95 V when more than 24 channels used | ||
| + | * We first change the regulator ⇒ same problem | ||
| + | * **''Routing issue:''** Strip line from regulator to FPGA too resistive ⇒ bring directly the 1.1 V to the FPGA ⇒ SOLVED | ||
| + | |||
| + | ===== First firmwares tested ===== | ||
| + | |||
| + | ==== Mapping ==== | ||
| + | |||
| + | |PCB 44 strips|FE2PR|PR|PR_IN|remap|TDC| | ||
| + | |T1|back21|1|CH21|B10|0| | ||
| + | |B1|back20|1|ch20|A10|1| | ||
| + | |T2|back23|1|ch23|E10|2| | ||
| + | |B2|back22|1|ch22|D10|3| | ||
| + | |T3|back25|1|ch25|A11|4| | ||
| + | |B3|back24|1|ch24|F10|5| | ||
| + | |T4|back27|1|ch27|D11|6| | ||
| + | |B4|back26|1|ch26|B11|7| | ||
| + | |T5|back29|1|ch29|A12|8| | ||
| + | |B5|back28|1|ch28|F11|9| | ||
| + | |T6|back31|1|ch31|D12|10| | ||
| + | |B6|back30|1|ch30|D15|11| | ||
| + | |T7|front17|1|ch1|A2|12| | ||
| + | |B7|Front16|1|ch0|C1|13| | ||
| + | |T8|front19|1|ch3|B3|14| | ||
| + | |B9|front18|1|ch2|A3|15| | ||
| + | |T9|front21|1|ch5|B5|16| | ||
| + | |B9|front20|1|ch4|A5|17| | ||
| + | |T10|front23|1|ch7|B6|18| | ||
| + | |B10|front22|1|ch6|A6|19| | ||
| + | |T11|front26|1|ch10|C7|20| | ||
| + | |B11|front24|1|ch8|C6|21| | ||
| + | |T12|Front31|1|ch15|C8|22| | ||
| + | |B12|front28|1|ch12|E7|23| | ||
| + | |T13|back5|2|ch21|A28|24| | ||
| + | |B13|back4|2|ch20|B28|25| | ||
| + | |T14|back7|2|ch23|D29|26| | ||
| + | |B14|back6|2|ch22|E29|27| | ||
| + | |T15|back9|2|ch25|B29|28| | ||
| + | |B15|back8|2|ch24|C29|29| | ||
| + | |T16|back11|2|ch27|E30|30| | ||
| + | |B16|back10|2|ch26|F30|31| | ||
| + | |T17|back13|2|ch29|B30|32| | ||
| + | |B17|back12|2|ch28|D30|33| | ||
| + | |T18|back15|2|ch31|B31|34| | ||
| + | |B18|back14|2|ch30|C31|35| | ||
| + | |T19|front1|2|ch1|B24|36| | ||
| + | |B19|front0|2|ch0|D24|37| | ||
| + | |T20|Front3|2|ch3|E25|38| | ||
| + | |B20|front2|2|ch2|F25|39| | ||
| + | |T21|front5|2|ch5|B25|40| | ||
| + | |B21|front4|2|ch4|D25|41| | ||
| + | |T22|front7|2|ch7|F26|42| | ||
| + | |B22|front6|2|ch6|A25|43| | ||
| + | |T23|front10|2|ch10|B26|44| | ||
| + | |B23|front8|2|ch8|D26|45| | ||
| + | |T24|front14|2|ch14|D27|46| | ||
| + | |B24|front12|2|ch12|F27|47| | ||
| + | |||
| + | |||
| + | **''Carefull: The 2 chips don't have the same mapping''** | ||
| + | ==== 48 channels latched (rising edge only) ==== | ||
| + | |||
| + | === Pedestals === | ||
| + | |||
| + | == FEBv2_1 channel per channel 745460 == | ||
| + | |||
| + | {{ :oct2018:run745460_allstrip2_1.png?600 |}} | ||
| + | |||
| + | {{ :oct2018:run745460_allstrip2_2.png?600 |}} | ||
| + | |||
| + | == FEBv2_7 channel per channel 745463 == | ||
| + | |||
| + | {{ :oct2018:run745463_allstrip2_1.png?600 |}} | ||
| + | |||
| + | {{ :oct2018:run745463_allstrip2_2.png?600 |}} | ||
| + | |||
| + | == FEBv2_8 channel per channel 745464 == | ||
| + | |||
| + | {{ :oct2018:run745464_allstrip2_1.png?600 |}} | ||
| + | |||
| + | {{ :oct2018:run745464_allstrip2_2.png?600 |}} | ||
| + | |||
| + | == FEBv2_8 all channels 745465 == | ||
| + | |||
| + | {{ :oct2018:run745465_allstrip2_1.png?600 |}} | ||
| + | |||
| + | {{ :oct2018:run745465_allstrip2_2.png?600 |}} | ||
| + | |||
| + | ==== Injection tests ==== | ||
| + | === Injection board === | ||
| + | |||
| + | It is functionnal but no possibility to modulate the FPGA output voltage ⇒ No pedestal/gain curve. Patch with additional buffers will be tested soon | ||
| + | |||
| + | Time calibration feasible. | ||
| + | |||
| + | ==== 2018/11/09 Status & plans ==== | ||
| + | |||
| + | * ''Debugging Petiroc FSM'' (deadlock). Lengthly due to compilation time with 48 channels (2h) | ||
| + | | ||
| + | * ''Next week'': | ||
| + | |||
| + | * Complete time calibration | ||
| + | * Re test ToT version | ||
| + | * Transfer the board to Cern and connect it on the return chamber (additional boards are still in cabling since some components are now missing in the cabling company) | ||
| + | * Repeat noise and calibration tests | ||
| + | * Check efficiency curves and position resolution | ||
| + | |||
| + | |||
| + | * ''Before Xmas break'': | ||
| + | |||
| + | |||
| + | * Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs) | ||
| + | * Re submit the board with all corrections | ||
| + | * Confirm all the fixes before submitting V2 | ||
| + | * Will be used for R&D RPCs | ||
| + | |||
| + | |||
| + | ==== 2018/11/11 Debugging ==== | ||
| + | |||
| + | |||
| + | Still unstable PETIROC FSM with 48 channels | ||
| + | |||
| + | * Working with small time window or with low rate, dead lock in all other cases | ||
| + | * Working with 16 channels | ||
febv1_debug.1541674154.txt.gz · Last modified: 2021/07/10 23:20 (external edit)
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