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Summary of FEB version 1 debugging

Schematic issues

Missing control signals on regulator ⇒ by passed hardwarely
One missing pull up on NOR32 per ASIC ⇒ Fixed externally
HDMI signals direction ⇒ Use alternative signal entries on FPGA and patch MDCC accordingly
11 Mhz calibration clock missing ⇒ oscillator added on spare entry
Jitter-cleaner chip unstability ⇒ By passed, used either an additional 40 Mhz oscillator or MDCC clock directly

Signal TAP (multi channels internal logic analyzer) unstabilties
- Initially we thought it is firmware related. Lot of time lost in trying to understand fluctuant behaviours
Identified the source to a 400 MHz clock unstabilities ⇒ Internal to the FPGA
Vcc core drops from 1.1 V to 0.95 V when more than 24 channels used
- We first change the regulator ⇒ same problem
- Routing issue: Strip line from regulator to FPGA too resistive ⇒ bring directly the 1.1 V to the FPGA ⇒ SOLVED