febv1_debug
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Summary of FEB version 1 debugging
Schematic issues
- Missing control signals on regulator ⇒ by passed hardwarely
- One missing pull up on NOR32 per ASIC ⇒ Fixed externally
- HDMI signals direction ⇒ Use alternative signal entries on FPGA and patch MDCC accordingly
- 11 Mhz calibration clock missing ⇒ oscillator added on spare entry
- Jitter-cleaner chip unstability ⇒ By passed, used either an additional 40 Mhz oscillator or MDCC clock directly
febv1_debug.1541674154.txt.gz · Last modified: 2021/07/10 23:20 (external edit)
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