Differences

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--- febv1_debug [2018/11/09 04:50]
acqilc
+++ febv1_debug [2021/07/10 23:21] (current)
@@ Line 106: / Line 106: @@
 === Injection board ===
- It is functionnal but no possibility to modulate the FPGA output voltage ⇒ No pedestal/gain
+ It is functionnal but no possibility to modulate the FPGA output voltage ⇒ No pedestal/gain curve. Patch with additional buffers will be tested soon
+Time calibration feasible.
+====  2018/11/09 Status & plans ====
+ * ''Debugging Petiroc FSM'' (deadlock). Lengthly due to compilation time with 48 channels (2h)
+ * ''Next week'':
+    * Complete time calibration
+    * Re test ToT version
+    * Transfer the board to Cern and connect it on the return chamber (additional boards are still in cabling since some components are now missing in the cabling company)
+      * Repeat noise and calibration tests
+      * Check efficiency curves and position resolution
+ * ''Before Xmas break'':
+    * Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs)
+    * Re submit the board with all corrections
+      * Confirm all the fixes before submitting V2
+      * Will be used for R&D RPCs
+====  2018/11/11 Debugging ====
+Still unstable PETIROC FSM with 48 channels
+  * Working with small time window or with low rate, dead lock in all other cases
+  * Working with 16 channels

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