Conditions in beam dump area:

We are using air fan cooling. The FEBs are covered with copper cooling plates that takes the ground from patch panel. The chamber is grounded through patch panel to the common ground. For now we use the table top LV power supplies. The chamber is under stable gas since several weeks.

The front board with petiroc 2c is currently located in the bottom position hence it is reading data with beam. The beam position is at the moment can only be read with the front end board with petiroc 2b. Once we finish the calibration, noise studies of the petiroc 2c, we will rotate the chamber so that we can collect data with muons.

1. First calibration test on chamber for petiroc 2c is performed with HV OFF.
   

enable_delay_reset_trigger(4) is set for all the asics.

More details, together with pictures can be found in the following directories:

This is the base directory of the code: /home/acqcmsmu/FEB_DAQ/python_src_BC0id_01092021/python_src_BC0id
The obtained dac6b configuration is in this folder inside base : dac6bConfig_petiroc2c_188_feb6_HVOFF
The SingleChannelEqualization Plots are here: SingleChannelEqualizationPlots_petiroc2c_188_feb6_HVOFF
The Data in terms of csv files are here: SweepData_petiroc2c_188_feb6_HVOFF
All the plots of all the iterations for each channel can be found here : Plots_petirocC_petiroc2c_188_feb6_HVOFF

• Reset set to 4

After obtaining channel by channel 6b dac and 10 b dac, we enable all channels and reobtain scurves using the already produced 6b dac values.
The Data in terms of csv files are here: SweepData_AllChannelsEn_petiroc2c_188_feb6_HVOFF/

Examples of SCurve obtained can be seen on the followoing picture (FPGA 0/TOP)

One can extract the minimum threshold where the channel is not contineously on (Eff< 0.985) and the maximum threshold where it is above 0.5. The minimal corresponds to the pedestal adjustment actually set and the difference of the two is an estimation of picked/coherent noise. Results for all FPGA are in the following pictures

• FPGA 0 TOP, target 398

• FPGA 0 BOTTOM, target 383

• FPGA 1 TOP, target 419

• FPGA 1 BOTTOM, target 428

• FPGA 2 TOP, target 407

• FPGA 2 BOTTOM, target 388

The methodology is correct since we find back the assigned pedestal target value for all chips. The noise is of the order of 50 DAC10b

• Reset coditions changed

We changed the time window from 1 sec to 1 ms.
We changed the enable_delay_reset_trigger from 4 to 8.
The Data in terms of csv files are here: SweepData_AllChannelsEn_RT8_petiroc2c_188_feb6_HVOFF/

2 ) Step 1 with HV 5000 V. The elog is here:

3 ) Step 1 with HV 6500 V. The elog is here:

4 ) Step 1 with HV 7000 V. The elog is here:

5 ) Step 1 with HV 7200 V. The elog is here:

6 ) Step 1 with HV OFF, with auto reset delay 24ns:
We changed the enable_delay_reset_trigger from 4 to 8. 8*3ns = 24ns
LV power supply ground are connected to common braid 2V and 4 V in serial. Single Channels Equalisation is run again. The obtained dac6b configuration is in this folder inside base : dac6bConfig_petiroc2c_trigDelay8_188_feb6_HVOFF/
The SingleChannelEqualization Plots are here: SingleChannelEqualizationPlots_petiroc2c_trigDelay8_188_feb6_HVOFF/
The Data in terms of csv files are here: SweepData_petiroc2c_trigDelay8_188_feb6_HVOFF/

All channels enabled run :
csv data is saved here: SweepData_AllChannelsEn_TriggerDelay8_petiroc2c_188_feb6_HVOFF/

• FPGA 0 TOP , Target 397

• FPGA 0 BOTTOM , Target 383

• FPGA 1 TOP , Target 419

• FPGA 1 BOTTOM, Target 428

• FPGA 2 TOP, Target 407

• FPGA 2 BOTTOM , Target 387

7 ) Step 6 with HV OFF, with auto reset delay 12ns:
All channels enabled run :

• FPGA 0 TOP , Target 397

• FPGA 0 BOTTOM , Target 383

• FPGA 1 TOP , Target 419

• FPGA 1 BOTTOM, Target 428

• FPGA 2 TOP, Target 407

• FPGA 2 BOTTOM , Target 387

7) Step 1 with HV OFF, with auto reset delay 24ns:
We changed LV power supply from table top to caen. Only the all channels enabled s curved are measured. We obtain 4-5 dac unit less noise for each petiroc.