One main idea is to keep the possibility to replace the Master FPGA with an LpGBT chip on the final design So we need to use:

• elink data transmission
• I2C configuration

It is responsible of all communication, synchronisation and data formatting

The underlying protocol is provided by the CERN IP

The message structure is the following:

• 84 bits
• 82-83 : reserved
• 81-80: EC (unused)
• 0-79: 5 last payload long words (16 bits)
• Extra data:
  • 0-8: register address
  • 9-11: nword
  • 12-15: unused
  • 16-31: first payload long word

The message structure is the following:

• 84 bits
• 82-83 : reserved
• 81-80: EC (unused)
  • 0 never happens
  • 1 register response
  • 2 data
  • 3 never happens
• 0-79: 5 last payload long words (16 bits)
• Extra data:
  • If register response:
    • 0-8: register address
    • 9-11: nword
    • 12-15: unused
    • 16-31: first payload long word
  • if data:
    • 2 first payload words

No documentation, expected special data with 32 bits encoded (see CIC doc)

The GBT firmware should handle BC0 and RESYNC commands:

• BC0 genrate pulse (channel 0) and all TDC FPGA
• RESYNC resets counters on all TDCFPGA

• Data collection from the 3 EPort links
• Potentially:
  • T0 subtraction
  • Y measurement
  • Cluster reconstruction
• Data packaging and transfer to GBT

• 3 I2C buses with mechanism to write and read remote registers
• GBT interface

It should be simple but the GBT interface is not trivial.

We need to implement the block getting the BC0 from the start of the window and propagating back a BUSY. One line is also dedicated for RESYNC (no firmware)

There is also a TRIGGER line that should be connected to one TDC channel, but no firmware is needed

It's being implemented by Shirley, 3 separated sockets mechanism

• 10001 Slow control PETIROC
• 10002 Slow control TDC (calibration,masking,reset)
• 10003 Data

Each socket should have a block to decode incoming data to register and a block to encode outgoing buffer (packet structure)

Additional debug port , firmware can be inherited from SDHCAL (ILC) DIF boards