febv2_fw_req
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Table of Contents
FEBV2 Firmware structure and requirements
One main idea is to keep the possibility to replace the Master FPGA with an LpGBT chip on the final design So we need to use:
- elink data transmission
- I2C configuration
Master FPGA needs
It is responsible of all communication, synchronisation and data formatting
GBT communication
GBT synchronisation
Elink TDC reception
I2C slow control to TDC
Backup readout
DCC synchronisation
Wiznet (Ethernet) communication
FTDI (USB2) readout
TDC FPGA firmware
Elink TDC transmission
I2C slow control communication
TDC blocks
PETIROC FSM
febv2_fw_req.1558526687.txt.gz · Last modified: 2021/07/10 23:20 (external edit)
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