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test_febv2_petiroc2c [2021/11/02 10:41]
acqilc [Mesures au beam dump 02/11]
test_febv2_petiroc2c [2021/11/03 05:40] (current)
acqilc [Mesures au beam dump 02/11]
Line 155: Line 155:
  
 == FEB #6  Chambre 188 == == FEB #6  Chambre 188 ==
 +
 +The HV is set to 5 kV on both gaps. The LV is done with desk power supplies
  
 We do a first pedestal alignment channel / channel: We do a first pedestal alignment channel / channel:
Line 165: Line 167:
   P2C_resetDelay_parameter=4   P2C_resetDelay_parameter=4
  
 +Results are in:
  
 +  /​home/​acqcmsmu/​FEB_DAQ/​python_src_BC0id_01092021/​python_src_BC0id/​Results/​
 +  dac6bConfig_FEB6_188_single/​
 +  SweepData_FEB6_188_single/​
 +
 +With those settings we make a pedestal all channels ON run 1635856021966 in SweepData
 +
 +The sweep data files are in 
 +
 +  /​home/​acqcmsmu/​FEB_DAQ/​python_src_BC0id_01092021/​python_src_BC0id/​Results/​
 +  dac6bConfig_FEB6_188_all/​
 +  ​
 +The channels and summary png are in the same directory
 +
 +We observe a noise ~ 45-55 DAC10B counts (a bit high)
    
 +Here the turn on is around 455 and the target is 409 , so 45 DAC
 +
 +{{ :​petiroc2c:​scurve_channels_fpga_2_top_1635856021966.png |}}
 +
 +We repeat the run with different grounding ​ run 1635857964615
 +
 +Same results so we create a state in DB
 +
 +  RE41_188_FEB_6_BeamDump_LM
 +  ​
 +Version 2 is load with Scurve studies alignement and +60 from Target
 +
 +We then set the HV to 7.1 kV and try a run 1255 in /​data/​beamdump/​raw
 +
 + --- //​[[laurent.mirabito@gmail.com|DAQ user]] 2021/11/02 14:33//
 +For the moment no beam so difficult to conclude
 +
 +Few beam seen but weird trigger
 +
 +Run 1256 idem with good trigger but still weird data
 +
 +I create a "​bad"​ state with alignement with autoreset but FPGA reset settings it's version RE41_188_FEB_6_BeamDump_LM 3 
 +
 +Run 1257 is with this state, not a single channel seen except 32 (BC0) and 33 (Trigger)
 +
 + --- //​[[laurent.mirabito@gmail.com|DAQ user]] 2021/11/03 05:37//
  
 +State  RE41_188_FEB_6_BeamDump_LM 4 is identical with trehsold = Target +10
  
 +Lot of channels seen but only on FPGA 0 and first channels (0-10)
test_febv2_petiroc2c.1635849717.txt.gz · Last modified: 2021/11/02 10:41 by acqilc