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test_febv2_petiroc2c [2021/10/21 13:53] acqilc |
test_febv2_petiroc2c [2021/11/03 05:40] (current) acqilc [Mesures au beam dump 02/11] |
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* FPGA 2 BOTTOM , Target 387 | * FPGA 2 BOTTOM , Target 387 | ||
{{ :petiroc2c:scurve_summary_fpga_2_bottom_1634814414541.png?400 |Target 387}} | {{ :petiroc2c:scurve_summary_fpga_2_bottom_1634814414541.png?400 |Target 387}} | ||
+ | 7) Step 1 with HV OFF, with auto reset delay 24ns:\\ | ||
+ | We changed LV power supply from table top to caen. | ||
+ | Only the all channels enabled s curved are measured. | ||
+ | We obtain 4-5 dac unit less noise for each petiroc. | ||
+ | ==== Mesures au beam dump 02/11 ==== | ||
+ | |||
+ | === Organisation of code === | ||
+ | |||
+ | Gerald will patch the code in /home/acqcmsmu/FEB_DAQ/python_src_BC0id_01092021/python_src_BC0id | ||
+ | |||
+ | ToIncludeInEqualization.py | ||
+ | |||
+ | One should able to set the mode of Pedestal calculation: | ||
+ | |||
+ | * Single: True for channel/channel , False all channels ON | ||
+ | * p_type: Petiroc type 0:A 1:B 2:c | ||
+ | * r_type: Reset type, 0 FPGA Reset, 1 Autoreset (for PETIROC 2C only) | ||
+ | |||
+ | |||
+ | === Pedestal measurements === | ||
+ | |||
+ | == FEB #6 Chambre 188 == | ||
+ | |||
+ | The HV is set to 5 kV on both gaps. The LV is done with desk power supplies | ||
+ | |||
+ | We do a first pedestal alignment channel / channel: | ||
+ | |||
+ | p_type=2 # 0: A , 1: B , 2:C | ||
+ | p2C_autoreset_ON=True | ||
+ | single=True # scurve channel by channel or all channels at the same time | ||
+ | nDacTarget=-1 # -1 means find target automatically, otherwise put a DAC value to reach (example 400) | ||
+ | P2B_FSM_parameters=[3,2,2] | ||
+ | P2C_resetDelay_parameter=4 | ||
+ | |||
+ | Results are in: | ||
+ | |||
+ | /home/acqcmsmu/FEB_DAQ/python_src_BC0id_01092021/python_src_BC0id/Results/ | ||
+ | dac6bConfig_FEB6_188_single/ | ||
+ | SweepData_FEB6_188_single/ | ||
+ | |||
+ | With those settings we make a pedestal all channels ON run 1635856021966 in SweepData | ||
+ | |||
+ | The sweep data files are in | ||
+ | |||
+ | /home/acqcmsmu/FEB_DAQ/python_src_BC0id_01092021/python_src_BC0id/Results/ | ||
+ | dac6bConfig_FEB6_188_all/ | ||
+ | | ||
+ | The channels and summary png are in the same directory | ||
+ | |||
+ | We observe a noise ~ 45-55 DAC10B counts (a bit high) | ||
+ | |||
+ | Here the turn on is around 455 and the target is 409 , so 45 DAC | ||
+ | |||
+ | {{ :petiroc2c:scurve_channels_fpga_2_top_1635856021966.png |}} | ||
+ | |||
+ | We repeat the run with different grounding run 1635857964615 | ||
+ | |||
+ | Same results so we create a state in DB | ||
+ | |||
+ | RE41_188_FEB_6_BeamDump_LM | ||
+ | | ||
+ | Version 2 is load with Scurve studies alignement and +60 from Target | ||
+ | |||
+ | We then set the HV to 7.1 kV and try a run 1255 in /data/beamdump/raw | ||
+ | |||
+ | --- //[[laurent.mirabito@gmail.com|DAQ user]] 2021/11/02 14:33// | ||
+ | For the moment no beam so difficult to conclude | ||
+ | |||
+ | Few beam seen but weird trigger | ||
+ | |||
+ | Run 1256 idem with good trigger but still weird data | ||
+ | |||
+ | I create a "bad" state with alignement with autoreset but FPGA reset settings it's version RE41_188_FEB_6_BeamDump_LM 3 | ||
+ | |||
+ | Run 1257 is with this state, not a single channel seen except 32 (BC0) and 33 (Trigger) | ||
+ | |||
+ | --- //[[laurent.mirabito@gmail.com|DAQ user]] 2021/11/03 05:37// | ||
+ | |||
+ | State RE41_188_FEB_6_BeamDump_LM 4 is identical with trehsold = Target +10 | ||
+ | |||
+ | Lot of channels seen but only on FPGA 0 and first channels (0-10) |