test_febv2_petiroc2c
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test_febv2_petiroc2c [2021/11/02 15:38] acqilc [Mesures au beam dump 02/11] |
test_febv2_petiroc2c [2021/11/03 05:40] (current) acqilc [Mesures au beam dump 02/11] |
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| I create a "bad" state with alignement with autoreset but FPGA reset settings it's version RE41_188_FEB_6_BeamDump_LM 3 | I create a "bad" state with alignement with autoreset but FPGA reset settings it's version RE41_188_FEB_6_BeamDump_LM 3 | ||
| - | Run 1257 is with this state | + | Run 1257 is with this state, not a single channel seen except 32 (BC0) and 33 (Trigger) |
| + | --- //[[laurent.mirabito@gmail.com|DAQ user]] 2021/11/03 05:37// | ||
| + | State RE41_188_FEB_6_BeamDump_LM 4 is identical with trehsold = Target +10 | ||
| + | |||
| + | Lot of channels seen but only on FPGA 0 and first channels (0-10) | ||
test_febv2_petiroc2c.txt ยท Last modified: 2021/11/03 05:40 by acqilc
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