febv2_fw_req
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febv2_fw_req [2019/06/04 09:49] acqilc [Backup readout] |
febv2_fw_req [2021/07/10 23:21] (current) |
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| * I2C configuration | * I2C configuration | ||
| + | A bonus will be to have a first version of the SEU mitigation but it's not compulsory at this stage. | ||
| ===== Master FPGA needs ===== | ===== Master FPGA needs ===== | ||
| Line 111: | Line 112: | ||
| ==== EPort TDC transmission ==== | ==== EPort TDC transmission ==== | ||
| - | Data collection from all TDCs is done via a switch IP , Shirley is implementing it on FEBV1. | + | Data collection from all TDCs is done via a switch IP , a first version is being implemented on FEBV1. |
| The EPort IP should be part of the GBT-FPGA firmware from CERN and should be interfaced to the the switch. | The EPort IP should be part of the GBT-FPGA firmware from CERN and should be interfaced to the the switch. | ||
| - | BUSY is generated by an OR of all TDC channel (almost Full FIFO) | + | BUSY is generated by an OR of all TDC channel (almost Full FIFO) and should be propagated to Master FPGA |
| ==== I2C slow control communication ==== | ==== I2C slow control communication ==== | ||
| Line 135: | Line 136: | ||
| - | Shirley is working on those blocks for a new version of FEBV1 | + | Ongoing work on those blocks for a new version of FEBV1 |
| ==== PETIROC FSM ==== | ==== PETIROC FSM ==== | ||
febv2_fw_req.1559641747.txt.gz · Last modified: 2021/07/10 23:20 (external edit)
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