febv2_fw_req
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febv2_fw_req [2019/05/29 13:51] acqilc [Elink TDC transmission] |
febv2_fw_req [2021/07/10 23:21] (current) |
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| * I2C configuration | * I2C configuration | ||
| + | A bonus will be to have a first version of the SEU mitigation but it's not compulsory at this stage. | ||
| ===== Master FPGA needs ===== | ===== Master FPGA needs ===== | ||
| Line 57: | Line 58: | ||
| ==== GBT synchronisation ==== | ==== GBT synchronisation ==== | ||
| - | No documentation, expected special data with 32 bits encoded (see CIC doc) | + | No documentation found on GBT-FPGA, expected special data with 32 bits encoded (see CIC doc) |
| The GBT firmware should handle BC0 and RESYNC commands: | The GBT firmware should handle BC0 and RESYNC commands: | ||
| - | * BC0 genrate pulse (channel 0) and all TDC FPGA | + | * BC0 generate pulse (channel 0) and all TDC FPGA |
| * RESYNC resets counters on all TDCFPGA | * RESYNC resets counters on all TDCFPGA | ||
| Line 77: | Line 78: | ||
| * 3 I2C buses with mechanism to write and read remote registers | * 3 I2C buses with mechanism to write and read remote registers | ||
| - | * GBT interface | + | * GBT interface: |
| + | * decode incoming GBT frames to write I2C transfer | ||
| + | * encode I2C response to GBT frame | ||
| It should be simple but the GBT interface is not trivial. | It should be simple but the GBT interface is not trivial. | ||
| Line 92: | Line 95: | ||
| === Wiznet (Ethernet) communication === | === Wiznet (Ethernet) communication === | ||
| - | It's being implemented by Shirley, 3 separated sockets mechanism | + | It's being implemented currently but not yet tested, 3 separated sockets mechanism |
| * 10001 Slow control PETIROC | * 10001 Slow control PETIROC | ||
| Line 99: | Line 102: | ||
| Each socket should have a block to decode incoming data to register and a block to encode outgoing buffer | Each socket should have a block to decode incoming data to register and a block to encode outgoing buffer | ||
| - | (packet structure) | + | (packet structure) |
| === FTDI (USB2) readout === | === FTDI (USB2) readout === | ||
| - | Additional debug port , firmware can be inherited from SDHCAL (ILC) DIF boards | + | Additional debug port , firmware can be inherited from SDHCAL (ILC) DIF boards. It's a low priority |
| ===== TDC FPGA firmware ===== | ===== TDC FPGA firmware ===== | ||
| Line 109: | Line 112: | ||
| ==== EPort TDC transmission ==== | ==== EPort TDC transmission ==== | ||
| - | Data collection from all TDCs is done via a switch IP , Shirley is implementing it on FEBV1. | + | Data collection from all TDCs is done via a switch IP , a first version is being implemented on FEBV1. |
| The EPort IP should be part of the GBT-FPGA firmware from CERN and should be interfaced to the the switch. | The EPort IP should be part of the GBT-FPGA firmware from CERN and should be interfaced to the the switch. | ||
| - | BUSY is generated by an OR of all TDC channel (almost Full FIFO) | + | BUSY is generated by an OR of all TDC channel (almost Full FIFO) and should be propagated to Master FPGA |
| ==== I2C slow control communication ==== | ==== I2C slow control communication ==== | ||
| + | Pending block to the master FPGA one: | ||
| + | |||
| + | * Read/write local registers | ||
| + | * Triggers action already implemented on FEBV1 : | ||
| + | * PETIROC Slow control | ||
| + | * TDC calibration | ||
| + | * LUT readout | ||
| ==== TDC blocks ===== | ==== TDC blocks ===== | ||
| - | ==== PETIROC FSM ==== | + | Two parts: |
| + | * Single channel TDCs including TDL, encoder, LUT, output FIFO, interface to slow control | ||
| + | * Switch IP to collect all channels data from Output FIFO + generation of BUSY | ||
| + | |||
| + | |||
| + | Ongoing work on those blocks for a new version of FEBV1 | ||
| + | ==== PETIROC FSM ==== | ||
| + | Standalone block that mitigate the RESET of the latch on PETIROC. Copy from FEBV1 firmware | ||
febv2_fw_req.1559137902.txt.gz · Last modified: 2021/07/10 23:20 (external edit)
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